Method and apparatus for forming layout pattern of semiconductor integrated circuit

ABSTRACT

A method and an apparatus is provided for forming a layout pattern of a semiconductor integrated circuit comprising automatically reforming a layout pattern by only carrying out a routing process, when a required layout pattern is the same as an existing layout pattern at the transistor-constitution level. Further, a method or an apparatus is provided for forming a layout pattern of a semiconductor integrated circuit comprising automatically reforming a layout pattern without analyzing the logical information down to the transistor-constitution level, when a required layout pattern is not the same as an existing layout pattern in the transistor-constitution level. Therefore, processing can be simplified and operation speed can be increased.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method and an apparatus for forming alayout pattern of a semiconductor integrated circuit, more particularly,to a method and an apparatus for forming a layout pattern of asemiconductor integrated circuit using a cell generator whichautomatically forms a layout pattern of a large scale integrated circuit(LSI) to simplify processing and carry out high speed operation of thecell generator using layout information of an existing layout pattern.

2. Description of the Related Art

Recently, a CAD (computer aided design) tool such as a cell generatorfor automatically forming a hard mask of a gate array or a mask patternin a cell library of a standard cell LSI has been studied and improved.Furthermore a method for forming a layout pattern of a semiconductorintegrated circuit using the cell generator, is actively being studied.In the automatic forming processes of a layout pattern, automatic layouttechniques and automatic wiring techniques in a cell or a functionalblock have become advanced, and are now actually being used.

Generally, a functional block, such as a cell in a cell library of astandard cell LSI, is formed by a cell generator using logicalinformation, and the logical information, which includes connectioninformation and layout information, is indicated by a logical circuitdiagram or a programming language, i.e., a logical description language.Note, for example, information of a logical circuit diagram is processedin a CAD tool, that is, a logical circuit diagram is entered into theCAD tool and data of the logical circuit diagram is translated into alogical description language. A layout pattern of the functional blockis, for example, formed by the cell generator by inputting logicalinformation of a logical description language. Note, the logicalinformation of the logical description language may be directly producedor input by a human operator.

As described above, a layout pattern is automatically formed by carryingout the placement process and the routing process of thetransistor-constitution level. Note, the layout pattern obtained by thecell generator is not only one type but a plurality of types, and it isdifficult to obtain an optimum layout pattern from those plural layoutpatterns. Further, almost all layout patterns formed by the cellgenerator are larger size than a layout pattern formed by a person.Consequently, in practice, placement processing of small blocks ispreviously carried out by a person, and only the routing process iscarried out by a computer system, e.g., a cell generator.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a method and anapparatus for producing a semiconductor device which can simplifyprocessing in a cell generator and shorten the operation speed of thecell generator, and furthermore, to provide a method and an apparatusfor producing a semiconductor device which can automatically form arequired layout pattern by using only connection information of anexisting layout pattern without carrying out an input processing of alogical circuit diagram and forming a logical description language, ifan optimum layout is not found.

According to the present invention, there is provided a method offorming a layout pattern of a semiconductor integrated circuitcomprising, a step of analyzing logical information down to atransistor-constitution level and inputting the analyzed logicalinformation into a cell generator, and a step of automatically forming alayout pattern by carrying out a placement process and a routing processat the transistor-constitution level by the cell generator, wherein themethod further comprises, a step of automatically reforming a layoutpattern by only carrying out the routing process, when required logicalinformation is the same as existing logical information and a requiredlayout pattern is also the same as an existing layout pattern at thetransistor-constitution level, by inputting connection information andlayout information of the existing layout pattern into the cellgenerator.

The logical information may be indicated by a logical circuit diagram ora logical description language. The required layout pattern and theexisting layout pattern may be constituted by a plurality of basic cellsincluding a plurality of transistors.

A pattern of the transistor in the basic cell of the required layoutpattern may be different from that of the existing layout pattern. Agate length of the transistor in the basic cell of the required layoutpattern may be different from that of the existing layout pattern. Agate width of the transistor in the basic cell of the required layoutpattern may be different from that of the existing layout pattern.

The reformed layout pattern may be used to constitute a cell includingsome logic gates. The method may be applied to a cell generator using acomputer system.

Further, according to the present invention, there is also provided amethod of forming a layout pattern of a semiconductor integrated circuitcomprising, a step of analyzing logical information down to atransistor-constitution level and inputting the analyzed logicalinformation into a cell generator, and a step of automatically forming alayout pattern by carrying out a placement process and a routing processat the transistor-constitution level by the cell generator, wherein themethod further comprises, a step of automatically reforming a layoutpattern without analyzing the logical information down to thetransistor-constitution level, when required logical information is thesame as existing logical information but a required layout pattern isnot the same as an existing layout pattern at thetransistor-constitution level, by inputting connection information ofthe existing layout pattern into the cell generator.

The logical information may be indicated by a logical circuit diagram ora logical description language. The required layout pattern and theexisting layout pattern may be constituted by a plurality of basic cellsincluding a plurality of transistors.

A pattern of the transistor in the basic cell of the required layoutpattern may be different from that of the existing layout pattern. Aconstitution of the transistor in the basic cell of the required layoutpattern is different from that of said existing layout pattern.

The reformed layout pattern may be used for constituting a cellincluding some logic gates. The method may be applied to a cellgenerator using a computer system.

Furthermore, according to the present invention, there is also providedan apparatus for forming a layout pattern of a semiconductor integratedcircuit comprising, a unit for analyzing logical information indicatedby a logical circuit diagram or a logical description language down to atransistor-constitution level and inputting the analyzed logicalinformation into a cell generator, a unit for automatically forming alayout pattern by carrying out a placement process and a routing processof the transistor-constitution level by the cell generator, a firstreforming unit for automatically reforming a layout pattern by onlycarrying out the routing process, when required logical information isthe same as existing logical information and a required layout patternis also the same as an existing layout pattern at thetransistor-constitution level, by inputting connection information andlayout information of the existing layout pattern into the cellgenerator, and a second reforming unit for automatically reforming alayout pattern without analyzing the logical information down to thetransistor-constitution level, when required logical information is thesame as existing logical information but a required layout pattern isnot the same as an existing layout pattern at thetransistor-constitution level, by inputting connection information ofthe existing layout pattern into the cell generator.

The logical information may be indicated by a logical circuit diagram ora logical description language. The required layout pattern and theexisting layout pattern may be constituted by a plurality of basic cellsincluding a plurality of transistors.

The first reforming unit may automatically reform a layout pattern byonly the routing process, even if a pattern of the transistor in thebasic cell of the required layout pattern is different from that of theexisting layout pattern. The first reforming unit may automaticallyreform a layout pattern by only the routing process, even if a gatelength of the transistor in the basic cell of the required layoutpattern is different from that of the existing layout pattern. The firstreforming unit may automatically reform a layout pattern by only therouting process, even if a gate width of the transistor in the basiccell of said required layout pattern is different from that of saidexisting layout pattern.

The second reforming unit may automatically reform a layout patternwithout analyzing the logical information down to thetransistor-constitution level, when a constitution of the transistor inthe basic cell of the required layout pattern is different from that ofthe existing layout pattern.

The reformed layout pattern may be used for constituting a cellincluding some logic gates. The apparatus is applied as a cell generatorin a computer aided design system.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more clearly understood from thedescription of the preferred embodiments as set forth below withreference to the accompanying drawings, wherein:

FIG. 1 is a schematic diagram indicating processes of a cell generatoraccording to the prior art;

FIG. 2 is a diagram indicating an example of a logical circuit forinputting logical information to the cell generator;

FIG. 3 is a diagram indicating an example of a logical descriptionlanguage for inputting logical information into the cell generator;

FIG. 4 is a diagram indicating an example of a layout pattern generatedin accordance with the logical information of the logical circuit or thelogical description language;

FIG. 5 is a flowchart indicating processes of a program for the cellgenerator according to the prior art;

FIGS. 6A to 6D are diagrams indicating various transistor-constitutionsin half of a basic cell;

FIG. 6E is a circuit diagram of the transistor-constitutions shown inFIGS. 6A to 6D;

FIG. 6F is diagram indicating transistor-constitutions in half of abasic cell which is a different transistor-constitution from that shownin FIGS. 6A to 6D;

FIG. 6G is a circuit diagram of the transistor-constitution shown inFIG. 6F;

FIG. 7 is a diagram indicating a variation of the layout pattern shownin FIG. 4;

FIG. 8A is a flowchart indicating processes of a program for a cellgenerator according to the present invention;

FIG. 8B is a flowchart indicating processes in an extracting processshown in FIG. 8A;

FIG. 8C is a flowchart indicating processes in an automatic routingprocess shown in FIG. 8A;

FIG. 9A is a diagram indicating a transistor-constitution in an exampleof a basic cell;

FIG. 9B is a diagram indicating transistor connections in the basic cellshown in FIG. 9A;

FIG. 10A is a diagram indicating an example of a logical circuit;

FIG. 10B is a diagram indicating a transistor-constitution in thelogical circuit shown in FIG. 10A; and

FIG. 10C is a diagram for indicating terminal connections in the logicalcircuit shown in FIG. 10A.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

For a better understanding of the preferred embodiments of the presentinvention, the problems of the related art will be explained first.

Conventionally, CAD tools such as a cell generator have been studied andprovided. FIG. 1 is a schematic diagram indicating the processes of acell generator according to the prior art. Generally, in a cellgenerator, input data of the cell generator is logical informationindicated by a logical circuit diagram or a logical descriptionlanguage. Namely, as shown in FIG. 1, in a method for forming a layoutpattern of a semiconductor integrated circuit using the cell generatoraccording to the prior art, the logical information is analyzed down toa transistor-constitution level and the analyzed logical information isinput into the cell generator, and layout data (a layout pattern) isautomatically formed by a placement process and a routing process by thecell generator. Note, the logical information, which may be called a NETLIST, includes connection information and layout information.

FIG. 2 is a diagram indicating an example of a logical circuit forinputting logical information into the cell generator, FIG. 3 is adiagram indicating an example of a logical description language forinputting logical information into the cell generator, and FIG. 4 is adiagram indicating an example of a layout pattern generated inaccordance with the logical information of the logical circuit or thelogical description language.

As described above, a functional block, e.g., a cell in a cell libraryof a standard cell LSI is, for example, formed by the cell generator byusing logical information indicated in a logical circuit diagram asshown in FIG. 2 or a logical description language as shown in FIG. 3.Note, the logical circuit diagram as shown in FIG. 2 is, for example,entered into a CAD tool and data of the logical circuit diagram istranslated into the logical description language as shown in FIG. 3.Next, for example, a layout pattern of the cell is formed by the cellgenerator by inputting logical information of a logical descriptionlanguage. Note, the logical information of the logical descriptionlanguage may be generated not only by the CAD tool by translating thedata of the logical circuit diagram, but also directly produced or inputby a human operator.

As described above, the layout pattern shown in FIG. 4 is automaticallyformed by carrying out the placement process and the routing process atthe transistor-constitution level. Note, the obtained layout pattern ofthe cell, which is output data of the cell generator, is not only of onetype but a plurality of types, since plural types of layout patterns canbe formed by the cell generator. In these plural layout patterns, aspace occupied by one layout pattern is not the same as that of anotherlayout pattern, and it is difficult to obtain an optimum layout patternfrom those plural layout patterns. Further, almost all layout patternsformed by the cell generator are larger in size than a layout patternformed by a person. Consequently, in practice, placement processing ofsmall blocks is previously carried out a person, and only the routingprocess is carried out a computer system, e.g., a cell generator.

FIG. 5 is a flowchart indicating processes of a program for the cellgenerator according to the prior art, and references P₁, P₂, and P₃denote steps in the flow.

First, in the step P₁, a placement process is carried out forpositioning a transistor at a suitable point. In the step P₂, after thisplacement process, a routing process for connection between theterminals of the transistors is carried out. Note, in the conventionalart for forming a layout pattern of a semiconductor integrated circuit,the layout pattern is not formed in practice by a placement process at atransistor-constitution level by the cell generator, but is formed bydefining functional blocks as shown in FIG. 2 and carrying out a routingprocess between the defined blocks. Further, the routing process hasseveral variations, for example, the wiring configuration can bemodified by changing a sequence in the routing process. Therefore, therouting process is carried out including various factors of the wiringsequence and the like.

Next, in the step P₃, the formed layout pattern of the cell (functionalblock) in the cell generator is evaluated. In the step P₃, when a layoutpattern of the cell is decided to be satisfactory (OK), the process iscompleted. Conversely, in the step P₃, when wiring portions of thelayout pattern formed by the cell generator are not satisfactorily wired(NG), the step P₁ is returned to improve the wiring portions so thatthey are wired in a more orderly manner. Therefore, in order to obtainan optimum cell layout, the above processes should be repeatedly carriedout to feed-back information for improvement (for example, tens ofthousands times or hundreds of thousands times). However, in practice,the layout pattern of a cell formed by a person is much better than thatof a cell formed by a computer system, even if the above processes arecarried out many times in the computer system.

As described above, in the conventional art for forming a layout patternof a semiconductor integrated circuit, if the above processes arecarried out repeatedly in the computer system or the cell generator, asatisfactory layout pattern or an optimum cell layout pattern cannot bealways formed, processing time may be quite long, and a layout patternof a cell formed by using a computer system or a cell generator, may notactually be used. Namely, software or a computer program for the cellgenerator cannot automatically form an optimum cell layout pattern.

Incidentally, in forming a cell layout pattern using a cell generator,targets of the cell generator can be roughly divided into the followingtwo cases.

(I) A case in which a layout pattern is newly formed by analyzing arequired logical circuit diagram for the purpose of adding a new cell toa cell library or providing a new custom LSI and the like.

(II) A case in which a layout pattern is reformed by providing highdensity and large scale integration. For example, when a predeterminedtransistor size is changed to a smaller size, for example, a basictransistor size in a basic cell is made smaller in accordance with animprovement in the producing art of semiconductor devices, a layoutpattern of a functional block or a cell may be reformed. Particularly,when the shape of a transistor is changed, a previously used layoutpattern (an existing layout pattern) of the cell should be entirelyreformed. However, when only the size of a transistor is to be reduced,in some cases the existing layout pattern can be used by merely reducingthe existing layout pattern.

If a cell library is completely changed, generally, about 100˜200 kindsof layout patterns should be formed from the beginning.

Conventionally, a cell generator was equally used for the above twocases in accordance with the flow of processes shown in FIG. 5 withoutdividing the two cases, and thus the processing time of the cellgenerator was too long. Note, in case (II), the cell generator does notneed to carry out all of the processes, however, in case (I), the cellgenerator should completely carry out all of the processes of the flowfrom the beginning. Namely, in case (II), for example, when space forthe existing layout pattern is reduced by reducing the wiring size, orwhen the existing layout pattern is improved in accordance with atransistor shape in the basic cell, the cell generator need only carryout some of the processes shown in FIG. 5. However, in practice, thecell generator is equally used for the above two cases (I) and (II), theprocesses in the cell generator become extensive and the operation speedof the cell generator becomes too slow, and thus, in practice the layoutpattern of the cell is mainly formed by a person.

Next, the principle and embodiments of a method and an apparatus forforming a layout pattern of a semiconductor integrated circuit accordingto the present invention will be explained.

The present invention provides a method for forming a layout pattern ofa semiconductor integrated circuit comprising, a step for analyzinglogical information down to a transistor-constitution level andinputting the analyzed logical information into a cell generator, and astep for automatically forming a layout pattern by a placement processand a routing process at the transistor-constitution level by the cellgenerator, which steps are the same as in conventional method. Further,the method of the present invention comprises a step of automaticallyreforming a layout pattern by carrying out only the routing process,when required logical information is the same as existing logicalinformation and a required layout pattern is also the same as anexisting layout pattern at the transistor-constitution level, byinputting connection information and layout information of the existinglayout pattern into the cell generator, or a step of automaticallyreforming a layout pattern without analyzing the logical informationdown to the transistor-constitution level, when required logicalinformation is the same as existing logical information but a requiredlayout pattern is not the same as an existing layout pattern at thetransistor-constitution level, by inputting a connection information ofthe existing layout pattern into the cell generator. Note, in thepresent invention, the required logical information should be same asthe existing logical information, and thus the existing layout pattern,which is previously formed and used, can be utilized for reforming.

In the present invention, logical information extracted from theexisting layout pattern which is existing logical information comprisingconnection information and layout information, is input into the cellgenerator. Namely, when the required layout pattern has the sameconfiguration as the existing layout pattern, the connection informationand the layout information of the existing layout pattern are input intothe cell generator, and only a routing process is carried out by thecell generator and the placement process can be deleted in the cellgenerator. Further, when the transistor-constitution of the requiredlayout pattern is not the same as that of the existing layout pattern,the logical information of the existing layout pattern is input into thecell generator, the inputting process of the logical informationincluding the logical information can be deleted. However, the placementprocess and the routing process should be carried out by the cellgenerator. Consequently, processes in the cell generator become simpleand processing time in the cell generator becomes short.

Below, the present invention will be concretely explained with referenceto the accompanying drawings.

FIGS. 6A to 6D are diagrams indicating various transistor-constitutionsin half of a basic cell, FIG. 6E is a circuit diagram of thetransistor-constitutions shown in FIGS. 6A to 6D, FIG. 6F is diagramindicating transistor-constitutions in half of a basic cell which has adifferent transistor-constitution from that shown in FIGS. 6A to 6D,FIG. 6G is a circuit diagram of the transistor-constitution shown inFIGS. 6F, and FIG. 7 is a diagram indicating a variation of the layoutpattern shown in FIG. 4.

In the above description, when a transistor configuration of a requiredlayout pattern is quite different from an existing layout pattern, thepresent invention cannot be applied. In such a case, the processesexplained above with reference to FIGS. 1 to 5 will be repeatedlycarried out.

However, when required logical information is the same as existinglogical information and a required layout pattern is also the same as anexisting layout pattern at the transistor-constitution level, a cellgenerator applied to the present invention automatically reforms therequired layout pattern by only a routing process, by inputtingconnection information and layout information of the existing layoutpattern into the cell generator. Namely, an analyzing process ofanalyzing the logical information down to the transistor-constitutionlevel and a placement process can be deleted.

A case in which required logical information is the same as existinglogical information and a required layout pattern is also the same as anexisting layout pattern at the transistor-constitution level is, forexample, a case of varying the form a basic cell shown in FIG. 6A toeach of the basic cell shown in FIGS. 6B to 6D. Namely, patterns of thetransistors Q₁, Q₂, Q₃, Q₄ in each basic cell shown in FIGS. 6B to 6Dare different from that of the transistors Q₁, Q₂, Q₃, Q₄ in the basiccell shown in FIG. 6A.

Concretely, for example, the gate length of each transistor Q₁, Q₂, Q₃,Q₄ of the basic cell shown in FIG. 6B is longer than that of the basiccell shown in FIG. 6A. With regard to FIG. 6C, the gate width of eachtransistor Q₁, Q₂, Q₃, Q₄ of the basic cell shown in FIG. 6C isdifferent from that of the basic cell shown in FIG. 6A, and with regardto FIG. 6D, a shape of the gate electrode of each transistor Q₁, Q₂, Q₃,Q₄ of the basic cell shown in FIG. 6D is different from that of thebasic cell shown in FIG. 6A. Note, the basic cells shown in FIGS. 6A to6D are indicated by the same circuit diagram in thetransistor-constitution shown in FIG. 6E. Furthermore, the case thatrequired logical information is the same as existing logical informationand a required layout pattern is also same the as an existing layoutpattern in the transistor-constitution level is, for example, a case ofvarying form a grid distance (which indicates a minimum distance betweenneighboring wirings) of a layout pattern shown in FIG. 4 to that of alayout pattern in FIG. 7.

Next, when required logical information is the same as existing logicalinformation but a required layout pattern is not the same as an existinglayout pattern at the transistor-constitution level, a cell generatorapplied to the present invention automatically reforms the requiredlayout pattern without analyzing the logical information down to thetransistor-constitution level. Namely, an analyzing process of analyzingthe logical information down to the transistor-constitution level neednot be carried out.

A case that required logical information is the same as existing logicalinformation but a required layout pattern is not the same as an existinglayout pattern in the transistor-constitution level is, for example, acase of varying form a basic cell shown in FIG. 6A to a basic cell shownin FIG. 6F. The constitution of the transistor in the basic cell shownin FIG. 6F is different from that of the basic cell shown in FIG. 6A.Because source or drain terminals of the transistors Q₁₁, Q₁₂ and thetransistors Q₁₃, Q₁₄ are formed by dividing the same electrodes 213a,213b and 217a, 217b, however, the source or drain terminals of thetransistors Q₁, Q₂ and the transistors Q₃, Q₄ are formed by the sameelectrodes 203 and 207. Note, the basic cell shown in FIG. 6F is notindicated by the circuit diagram shown in FIG. 6E, but by the circuitdiagram shown in FIG. 6G.

As described above, for example, when a basic cell shown in FIG. 6A forconstituting a layout pattern of a semiconductor integrated circuit ischanged to each of the basic cells shown in FIGS. 6B to 6D, a requiredlayout pattern is automatically reformed by only a routing process byinputting connection information and layout information of an existinglayout pattern into a cell generator. Further, for example, when a basiccell shown in FIG. 6A for constituting a layout pattern of asemiconductor integrated circuit is changed to a basic cell shown inFIG. 6F, a required layout pattern is automatically reformed withoutanalyzing logical information down to the transistor-constitution levelby inputting connection information of an existing layout pattern into acell generator. Namely, a required layout pattern is easily produced byusing an existing layout pattern, even if the size or shape between therequired layout pattern and the existing layout pattern are not the sameand only the positional relationship of channel regions in thetransistors between the required layout pattern and the existing layoutpattern are the same.

Typically, the existing layout pattern is constituted by a basic cell.In practice, however, an existing layout pattern is almost always formedby a person, this formed layout pattern being nearly an optimum layoutpattern, and the formed layout pattern can be used as is when a fixedwiring is changed without changing the size and shape of a transistor.In the above described method, a placement process can be deleted fromthe processes in the flowchart shown in FIG. 5, and thus, processingtime can be greatly reduced by deleting a feed-back process and thenumber of non-connection portions can be held to a minimum by using theexisting layout pattern which was practically used.

Furthermore, when a transistor-constitution of a required layout patternis not the same as that of the existing layout pattern whose logicalinformation is used as input data of the cell generator, the abovelayout information cannot be used, but the connection information can beused. In this case, the processes in FIG. 5 are necessary for the cellgenerator, but a process of inputting a logical circuit diagram and aprocess of forming a logical description language, which are shown inFIGS. 2 and 3, are not necessary, and thus a CAD system using thepresent invention can be made more efficient. Additionally, when anoptimum layout is known, (for example, an optimum layout can be known byexperience by a designer and the like), the feed-back process of theflowchart in FIG. 5 can be deleted.

FIG. 8A is a flowchart indicating processes of a program for a cellgenerator according to the present invention, FIG. 8B is a flowchart forindicating processes in an extracting process shown in FIG. 8A, and FIG.8C is a flowchart for indicating processes in an automatic routingprocess shown in FIG. 8A.

In FIG. 8A, references P₁₁ and P₁₂ denote each step of the flow. First,existing layout data correspond to a mask pattern data of an existinglayout pattern is processed in a cell generator, and the flow proceedsto the step P₁₁.

Processing in the step P₁₁, as shown in FIG. 8B, will be explained next.First, in a step P₁₁₁, the mask pattern data for graphic data processingis changed, and next a step P₁₁₂, extracting a transistor by checkingfor overlapping of graphics between layers by using the changed data, iscarried out. Next, in a step P₁₁₃, a connection between transistors isrecognized by tracing a wire, and then moving to a step P₁₁₄ fordeciding whether processes regarding all data are completed. In the stepP₁₁₄, when it is decided that the processes for all data are completed,the flow proceeds to a step P₁₁₅ for changing data for a cell generator,and connection and layout information are obtained. In the step P₁₁₄,when it is decided that the processes for all data are not completed,the flow returns to the step P₁₁₂. Note, the connection information andthe layout information, which correspond to logical information of theexisting layout pattern analyzed down to a transistor-constitutionlevel, are stored in a file. Further, the connection information and thelayout information of the existing layout pattern (the extractedcircuit) are derived in accordance with a verifying method applied tothe conventional circuit extraction method. Namely, as shown in FIGS. 6Ato 6E, connection information at a transistor-constitution level can beextracted by a transistor pattern and a wiring pattern, and theconnection information at the transistor-constitution level onlyindicates connections between terminals of the transistors.

Next, a required layout pattern corresponding to mask pattern data isprocessed in the cell generator, and the flow proceeds to a step P₁₂.

Processing in the step P₁₂, as shown in FIG. 8C, will be explained next.First, in a step P₁₂₁, two points are selected, which are a start and anend points, of a wiring in the connection information obtained by thestep P₁₁, and next in a step P₁₂₂, coordinates of the two points aretransformed to coordinate values on an actual pattern. Next, in a stepP₁₂₃, wiring between the two points is automatically carried out, andnext in a step P₁₂₄, it is decided whether processes regarding allconnection information are completed. In the step P₁₂₄, when it isdecided that the processes for all connection information are completed,the flow proceeds to a step P₁₂₅ for changing wired data to an actual ora required mask pattern data, i.e., required pattern data. In the stepP₁₂₄, when it is decided that the processes for all connectioninformation are not completed, the flow returns to the step P₁₂₁. Note,the mask pattern data obtained by the step P₁₂ corresponds to layoutdata of the required layout pattern.

FIG. 9A is a diagram indicating a transistor-constitution in an exampleof a basic cell, FIG. 9B is a diagram indicating transistor connectionsin the basic cell shown in FIG. 9A, FIG. 10A is a diagram indicating anexample of a logical circuit, FIG. 10B is a diagram indicating atransistor-constitution in the logical circuit shown in FIG. 10A, andFIG. 10C is a diagram for indicating terminal connections in the logicalcircuit shown in FIG. 10A.

In FIG. 9A, reference numeral 11 denotes a basic cell including eighttransistors, that is, the basic cell is constituted by P-channel typetransistors Tr1, Tr2, Tr7 and Tr8, and N-channel type transistors Tr3,Tr4, Tr5 and Tr6. Note, the basic cell shown in FIG. 9A is formed byconnecting two blocks each having four transistors indicated in FIGS. 6Ato 6D, and a semiconductor integrated circuit is constituted by using aplurality of basic cells. As shown in FIG. 9A, the basic cell is formedonly by transistor patterns, and a logical circuit shown in FIG. 10A isformed by carrying out a routing process as shown in FIG. 10B. Note, inFIG. 9A, reference mark ◯ denotes a terminal of a transistor and eachreference numeral close to the mark ◯ denotes a terminal number of therespective transistor.

FIG. 9B is a list of transistors extracted by the transistorconfiguration in FIG. 9A. In this extracted list, references G and S/Ddenote a gate terminal and a source/drain terminal in each transistor,and the same connection portions are indicated by the same referencenumerals. For example, as shown in FIG. 9A, a terminal number 3 iscommonly connected to source/drain terminals of transistors Tr1 and Tr2,and thus, in the list shown in FIG. 9B, a numeral "3" is shown atportions crossing between one source drain terminal S/D and thetransistor Tr2 and the other source drain terminal S/D and thetransistor Tr1. Consequently, it can be understood from the list shownin FIG. 9B that the source drain terminals S/D of the transistor Tr1 andTr2 are commonly connected without reference to FIG. 9A. Additionally,for example, in FIG. 9A, a gate of the transistor Tr1 is commonlyconnected to a gate of the transistor Tr3, and thus, in the list shownin FIG. 9B, a numeral "3" is shown at portions crossing between a gateterminal G and the transistor Tr1 and the gate terminal G and thetransistor Tr3, respectively. Consequently, a logical circuit diagramconstituted by transistors of a plurality of basic cells, as indicatedin FIG. 9A, can be described by referring to a list of transistorconnections as shown in FIG. 9B. Note, logical information of anexisting layout pattern corresponds, for example, to the data indicatedin the list shown in FIG. 9B, and this logical information is input tothe cell generator. Further, when the size of transistors in a basiccell or the shape of the transistors and a configuration of thetransistor-configuration in the memory cell are not changed, the logicalcircuit diagram and the list of transistor connections can be used andconnection information of the existing layout pattern is input into thecell generator.

Incidentally, since the extracting process in the above step P₁₁ isgenerally carried out for the purpose of verifying a pattern formed by aperson, in a conventional case (most cases at the present time), theformed pattern is processed by using a circuit extracting program and acircuit shown in FIGS. 9A or 10B is extracted. Consequently, a newspecial device is not necessary when extracting connection informationand layout information from existing layout data.

In a practical design process of a layout pattern, a connecting processfor connecting each terminal of a transistor, which is known as arouting process, is only carried out when a transistor constitution of abasic layout is not changed. FIG. 10A is a logical circuit diagramincluding two NAND gates 12 and 13, and an OR gate 14. FIG. 10B is adiagram of transistor connections constituted by a block LC₂ includingthe NAND gate 12 and the OR gate 14, and a block LC₁ including the NANDgate 13 on two basic cells 101 and 102. In FIG. 10B, the basic cell 101is constituted by P-channel type transistors 111, 112, 117, and 118, andN-channel type transistors 113, 114, 115, and 116, and the basic cell102 is constituted by P-channel type transistors 121, 122, 127 and 128,and N-channel type transistors 123, 124, 125 and 126. Note, in FIG. 10B,reference marks ◯ and denote terminals of the transistors in the basiccells 101 and 102, and each of reference numerals 1 to 32 close to themarks ◯ and denotes a terminal number of the respective transistor.

During these terminals, terminals connected to power supplies V_(DD) andVss are shown by the mark , and an actual wiring line is shown by athick solid line. Note, in this embodiment, transistors 125 to 128 ofthe basic cell 102 are not used for the logical circuit diagram shown inFIG. 10A. Furthermore, the list shown in FIG. 10C indicates connectioninformation, of the logical information in a logical circuit having thetransistor-constitution shown in FIG. 10B. This connection informationindicates connection data between terminals of the transistors. In theabove descriptions, information obtained by extracting a circuit from alayout pattern only indicates connection informations between theterminals of specific numbers in the transistors. Concretely, in FIG.10C, the list indicates that terminals 2, 14, 16, 19, and 21 areconnected to the power supply V_(DD), and terminals 5, 7, and 18 arecommonly connected. As described above, the extracted information isonly connection information of terminals in the transistors shown inFIG. 10C. However, when the connection information of the terminals isobtained, only a connecting process need be carried out. Consequently,the connection information of the terminals is input to the cellgenerator, a layout of the transistors is not necessary, and a layoutpattern of the cell can be automatically formed by only a routingprocess in the cell generator.

As described above, for example, when a required layout pattern has thesame configuration as an existing layout pattern, connection informationand layout information of the existing layout pattern are input into acell generator, and only a routing process is carried out by the cellgenerator and a placement process can be deleted in the cell generator.Further, for example, when a transistor-constitution of a requiredlayout pattern is not the same as that of an existing layout pattern,logical information of the existing layout pattern is input into a cellgenerator, and an inputting process of the logical information includinglogical information can be deleted. However, a placement process and arouting process should be carried out by the cell generator.Consequently, processes in the cell generator become simple and,processing time in the cell generator becomes short. Concretely, in thecase that a layout pattern of a cell is formed in about tens minutesusing a CAD system including a cell generator in the prior art, thelayout pattern of the cell is formed in only about several seconds bythe present invention. In actual use, a cell library (for example,including about one hundred cell layout patterns) which can be reformedin a few hours by a CAD system using the present invention, would takesome months for a person using the prior art.

Many widely different embodiments of the present invention may beconstructed without departing from the spirit and scope of the presentinvention, and it should be understood that the present invention is notlimited to the specific embodiments described in this specification,except as defined in the appended claims.

We claim:
 1. A method of forming a layout pattern of a semiconductorintegrated circuit having regular transistor constitutions, said methodcomprising:a step of receiving logical information; a step ofautomatically forming the layout pattern by performing a placementprocess for determining relative positions of transistors and a routingprocess for determining wiring connections of the transistors at atransistor-constitution level; and a step of automatically reforming thelayout pattern forming a reformed layout pattern by only performing therouting process, when required logical information is the same asexisting logical information and a required layout pattern is also thesame as an existing layout pattern at the transistor-constitution level,using connection information and layout information of said existinglayout pattern.
 2. A method of forming a layout pattern of asemiconductor integrated circuit as claimed in claim 1, wherein saidlogical information is indicated by a logical circuit diagram.
 3. Amethod of forming a layout pattern of a semiconductor integrated circuitas claimed in claim 1, wherein said logical information is indicated bya logical description language.
 4. A method of forming a layout patternof a semiconductor integrated circuit as claimed in claim 1, whereinsaid required layout pattern and said existing layout pattern comprise aplurality of basic cells including a plurality of transistors.
 5. Amethod of forming a layout pattern of a semiconductor integrated circuitas claimed in claim 4, wherein a pattern of the plurality of transistorsin the plurality of basic cells of said required layout pattern isdifferent from that of said existing layout pattern.
 6. A method offorming a layout pattern of a semiconductor integrated circuit asclaimed in claim 5, wherein a gate length of each of the plurality oftransistors in the plurality of basic cells of said required layoutpattern is different from that of said existing layout pattern.
 7. Amethod of forming a layout pattern of a semiconductor integrated circuitas claimed in claim 5, wherein a gate width of each of the plurality oftransistors in the plurality of basic cells of said required layoutpattern is different from that of said existing layout pattern.
 8. Amethod of forming a layout pattern of a semiconductor integrated circuitas claimed in claim 1, wherein said reformed layout pattern is used forforming a cell including some logic gates.
 9. A method of forming alayout pattern of a semiconductor integrated circuit as claimed in claim1, wherein said cell generator is used in a computer aided designsystem.
 10. A method of forming a layout pattern of a semiconductorintegrated circuit having regular transistor constitutions, said methodcomprising:a step of receiving logical information; a step ofautomatically forming the layout pattern by performing a placementprocess for determining relative positions of transistors and a routingprocess for determining wiring connections of the transistors at atransistor-constitution level; and a step of automatically reforming thelayout pattern forming a reformed layout pattern without analyzing thelogical information down to the transistor-constitution level, whenrequired logical information is the same as existing logical informationbut a required layout pattern is not the same as an existing layoutpattern at the transistor-constitution level, using connectioninformation of said existing layout pattern.
 11. A method of forming alayout pattern of a semiconductor integrated circuit as claimed in claim10, wherein said logical information is indicated by a logical circuitdiagram.
 12. A method of forming a layout pattern of a semiconductorintegrated circuit as claimed in claim 10, wherein said logicalinformation is indicated by a logical description language.
 13. A methodof forming a layout pattern of a semiconductor integrated circuit asclaimed in claim 10, wherein said required layout pattern and saidexisting layout pattern comprise a plurality of basic cells including aplurality of transistors.
 14. A method of forming a layout pattern of asemiconductor integrated circuit as claimed in claim 13, wherein aconstitution of the plurality of transistors in the plurality of basiccells of said required layout pattern is different from that of saidexisting layout pattern.
 15. A method of forming a layout pattern of asemiconductor integrated circuit as claimed in claim 10, wherein saidreformed layout pattern is used for forming a cell including some logicgates.
 16. A method of forming a layout pattern of a semiconductorintegrated circuit as claimed in claim 10, wherein said cell generatoris used in a computer aided design system.
 17. An apparatus for forminga layout pattern of a semiconductor integrated circuit having regulartransistor constitutions, said method comprising:means for receivinglogical information and inputting said logical information to a cellgenerator; means for automatically forming a layout pattern byperforming a placement process for determining relative positions oftransistors and a routing process for determining wiring connections ofthe transistors at a transistor-constitution level; first reformingmeans for automatically reforming the layout pattern forming a reformedlayout pattern by only performing the routing process, when requiredlogical information is the same as existing logical information and arequired layout pattern is also the same as an existing layout patternat the transistor-constitution level, using connection information andlayout information of said exiting layout pattern; and second reformingmeans for automatically reforming the layout pattern forming thereformed layout pattern without analyzing the logical information downto the transistor-constitution level, when the required logicalinformation is the same as the existing logical information but therequired layout pattern is not the same as the existing layout patternat the transistor-constitution level, using connection information ofsaid existing layout pattern.
 18. An apparatus for forming a layoutpattern of a semiconductor integrated circuit as claimed in claim 17,wherein said logical information is indicated by a logical circuitdiagram.
 19. An apparatus for forming a layout pattern of asemiconductor integrated circuit as claimed in claim 17, wherein saidlogical information is indicated by a logical description language. 20.An apparatus for forming a layout pattern of a semiconductor integratedcircuit as claimed in claim 17, wherein said required layout pattern andsaid existing layout pattern comprise a plurality of basic cellsincluding a plurality of transistors.
 21. An apparatus for forming alayout pattern of a semiconductor integrated circuit as claimed in claim20, wherein said first reforming means automatically reforms a layoutpattern by only performing the routing process, even if the pattern ofeach of the plurality of transistors in the basic cells of said requiredlayout pattern is different from that of said existing layout pattern.22. An apparatus for forming a layout pattern of a semiconductorintegrated circuit as claimed in claim 21, wherein said first reformingmeans automatically reforms a layout pattern by only performing therouting process, even if the gate length of each of the plurality oftransistors in the plurality of basic cells of said required layoutpattern is different from that of said existing layout pattern.
 23. Anapparatus for forming a layout pattern of a semiconductor integratedcircuit as claimed in claim 21, wherein said first reforming meansautomatically reforms a layout pattern by only performing the routingprocess, even if the gate width of each of the plurality of transistorsin the plurality of basic cells of said required layout pattern isdifferent from that of said existing layout pattern.
 24. An apparatusfor forming a layout pattern of a semiconductor integrated circuit asclaimed in claim 20, wherein said second reforming means automaticallyreforms a layout pattern without analyzing the logical information downto the transistor-constitution level, when the constitution of each ofthe plurality of transistors in the plurality of basic cells of saidrequired layout pattern is different from that of said existing layoutpattern.
 25. An apparatus for forming a layout pattern of asemiconductor integrated circuit as claimed in claim 17, wherein saidreformed layout pattern is used for forming a cell including some logicgates.
 26. An apparatus for forming a layout pattern of a semiconductorintegrated circuit as claimed in claim 17, wherein said cell generatoris used in a computer aided design system.